Sign in

username:

password:



Not a member?

Search 68hc12



Search tips

Subscribe to 68hc12



Ads

68hc12 by Keywords

68HC1 | 812A4 | 9S12DP256 | Bootloader | CodeWarrior | D60A | Debugger | DP256 | ECT | EEPROM | EVB | Flash | HC1 | HCS12 | I2C | IAR | ICC1 | Interrupts | LCD | M68KIT912DP256 | MC9S12DP256 | MC9S12DP256B | Metrowerks | Motor | MSCAN | Multilink | PLL | Quadrature | SDI | SPI | Transceiver | XFC

Discussion Groups

68HC12

Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).

Search Results for "xfc"

  

Post a new Thread

HCS12D PLL Woes   [4 Articles]

Jonathan Masters - Jan 17 2008
Hi all, I am just upgrading a product and will for only the second time use the PLL. In the first instance, the clock was only multiplied up from 8MHz to 12.5MHz and I haven... HCS12D PLL Woes

Re: Bad flash?   [2 Articles]

dleatmot - Oct 24 2007
--- In 6...@yahoogroups.com, Donald E Haselwood wrote: > > Does the following indicate the flash is bad (or is it something else)? > > Part: MC9S12E128CPV Mask 2L15... Re: Bad flash?

Re: S12D/E pad layout   [2 Articles]

dleatmot - Jul 19 2007
Hi James, That layout in the datasheet is a "best practice" layout. Trying to make the best of all worlds (ATD, Crystal, PLL, etc.)and fit it all onto a single layer. I ag... Re: S12D/E pad layout

Re: Flash sector erase on S12DP256B   [5 Articles]

Steve Russell - Oct 26 2006
Adrian, Some notes on further straws below. My reading of all this is that the units did not fail in the middle of operation, but failed only on power up. Is this correc... Re:  Flash sector erase on S12DP256B

Re: PLL - how to tie signals if not used   [3 Articles]

Doron Fael - Feb 5 2006
Robert, The official Freescale recommendation is to connect the Xfc pin to VDDPLL if the internal PLL is not used. Hope this helps, Doron Nohau HC12 In-Circuit Emulators www.... Re:  PLL - how to tie signals if not used

RE: MC9S12DG256B vs. MC9S12DG256

Honnold John-r37277 - Jan 20 2006
Jeff: The header files for the 'B' version and non 'B' versions is the same, so this should not be your issue. I double checked the errata, but nothing stands out that ... RE:  MC9S12DG256B vs. MC9S12DG256

MC9S12DP512 oscillator questions   [3 Articles]

Kent Williams - Mar 23 2005
Hi, I'm designing a board for a uni project using the MC9S12DP512 part. Everything is coming along well, except I've got a few questions about the oscillator s... MC9S12DP512 oscillator questions

Re: HCS12 prototype

Peter Lissenburg - Feb 1 2005
I think the docs are very short on sample/example circuits. The Vdd1/Vdd2 pins should be connected to caps, it is possible to drive the core with 2.5v applied to t... Re:  HCS12 prototype

Strange clock problem   [8 Articles]

Charles E. Scharlau - Aug 11 2004
I'm using an M9S12A64 microprocessor with a Pierce crystal clock circuit running at 4 MHz. I can see a beautiful, clean, stable, 4 MHz clock signal on the EXTAL and... Strange clock problem

Re: Why I can't use the PLL in MC9S12DP256B in Normal Single-Chip Mode

Doron Fael - Jul 22 2004
There is a problem that the LOCK bit sometimes reports that the PLL is locked and can be selected, where in fact it is not yet locked. (in other words the lock... Re:  Why I can't use the PLL in MC9S12DP256B in Normal Single-Chip Mode

Re: speed

Doron Fael - Jul 7 2004
You can increase the internal bus speed by programming the PLL registers (SYNR and REFDV registers) and engaging the PLL (in the CLKSEL register). The maximu... Re:  speed

Re: Re: new BDM multilink   [2 Articles]

Steve Russell - May 13 2004
At 05:17 PM 5/13/2004, Bill T. wrote: >My board is pretty dense, and I don't have enough space to literally >reproduce Motorola's "recommended" layout, although... Re:  Re: new BDM multilink

Re: How much clock variance can BDM's tolerate?

Steve Russell - May 12 2004
At 04:43 PM 5/12/2004, Bill T. wrote: >I'm working on a 9s12 project that requires an accurate 115200 baud >SCI. I want to run the 9s12 PLL at 22.1182 mHz, which gi... Re:  How much clock variance can BDM's tolerate?

Any issues with driving 9s12's with an oscillator?   [2 Articles]

tonalbuilder2002 - May 9 2004
Problems here with my first 9S12 board, was wondering if this sounds familiar to anybody... I have a new MC9S12DJ64CPV design that I'm driving with an 8mHz, 5 ... Any issues with driving 9s12's with an oscillator?

Stuck in "Self Clock Mode"

cleancontrollers - Apr 4 2004
Code ran fine on 68hc9sC32 eval board. In fact the PLL init code I'm using was lifted from the eval kit. After changing register include file, REFDV and SYNR I l... Stuck in "Self Clock Mode"

Re: Clock oscillator question   [2 Articles]

Oliver Betz - Mar 25 2004
Doron Fael <> wrote: [...] > Then, after all the above discussion, I believe it would be easier for > you to use a lower frequency crystal or clock generato... Re:  Clock oscillator question

Re: About m68evb912c32 evaluation board   [2 Articles]

zeta_alpha2002 - Jan 14 2004
For experiment, change the crystal to 8 MHz to see if it is better. --- In , "Zámbó Béla" wrote: > Hello, > Thank You for the idea... > I use Pi... Re: About m68evb912c32 evaluation board

Re: hc912D60 clock 1/2 Xtal?   [2 Articles]

Doron Fael - Dec 21 2003
Hello Wade, First of all you need to have VDDPLL connected to 5V, to allow the PLL to be engaged. You also need a network of two capacitors and a resistor to be... Re:  hc912D60 clock 1/2 Xtal?

Re: SCI baud rate.

Gordon Doughman - Oct 20 2003
With your 16 MHz crystal, & an 8 MHz bus speed, you can use the on-chip PLL to increase the bus speed to 24 MHz where you can obtain a baud rate of 115200. A valu... Re:  SCI baud rate.

Re: Trap on Unimplemented ISR   [2 Articles]

Doron Fael - Oct 12 2003
Theo, The PLL Loop Filter is the name of a network of 2 capacitors and one resistors that should be connected to the Xfc pin of your HC12 / HCS12, if you wan... Re: Trap on Unimplemented ISR

RE: BIG Question: Crystal Clock Generation on 9S12DP256

Dunnett Mark-R60287 - May 7 2003
Hello Group, As a Motorola FAE I have seen the question about using an external clock on S12 devices a number of times. I checked with my colleagues at TSPG Applic... RE:  BIG Question: Crystal Clock Generation on 9S12DP256

Re: Problem of reset with 9S12DG256

Steve Russell - Feb 28 2003
About the PLL: It's easy to program, but there are a some obscure points: PLL Filter ---------- You MUST put 2 capacitors and a resistor on the XFC pin... Re:  Problem of reset with 9S12DG256

RE: D60A clock issue (is it a Timer or PLL problem ?)

K.P.Venu - Nov 14 2002
Darci, The "slow problem" was present from Power ON itself. I'm not writing any thing to PLLCR, it's in the RESET state with PLLON bit set. (VDDPLL is high on pow... RE:  D60A clock issue (is it a Timer or PLL problem ?)

Re: XFC filter question   [5 Articles]

Michael J Huslig - Nov 12 2002
Gordon, What then is the function of Tbus mentioned in several spots in the lit when calculating FCLKDIV and ECLKDIV. Mike ----- Original Message -----... Re:  XFC filter question

Pierce Oscillator Configuration   [6 Articles]

Adrian Vos - Nov 11 2002
Hi All, I have just received a PCB back that I designed to use the S12DP256. I am putting the first unit togeather currently and having some problems getting a... Pierce Oscillator Configuration

XFC Loopfilter C and R values   [3 Articles]

Adrian Vos - Nov 8 2002
Hi All, Is anyone able to help me out with the setting of the Capacitor/resistor values for the PLL loop filter (going to the XFC pin) on the S12DP256. I am... XFC Loopfilter C and R values

New to S12DP256   [2 Articles]

Adrian Vos - Oct 28 2002
Hi All, I am doing a new project using the S12DP256 for the first time. I have used various other Motorola Micros in the past, but I am having trouble finding basi... New to S12DP256

MC912D60A question   [5 Articles]

Alar Lepp - Jul 26 2002
Hi all! Has anybody experience with such a strange behaviour of MC912D60ACPV8, mask 2K38K: I have two identical boards with D60A (single-chip mode). Both are a... MC912D60A question

Three component PLL network useless?   [8 Articles]

Oliver Betz - Jul 13 2002
Hi All, anybody out there with some knowledge of the D60(A) PLL behaviour? I think the three component (R+C)||C network is not better than a single capacit... Three component PLL network useless?

RE: [Mot-68hc12-list] RE: BDM mode and ccts, flash volta ges, AD questions   [3 Articles]

Kellogg Dave - Jun 12 2002
I have been getting this message every couple of hours for a couple of days now.  Is anyone else suffering the same?   D...@RaymondCorp.com 6... RE: [Mot-68hc12-list] RE:  BDM mode and ccts, flash volta ges, AD questions

BDM mode and ccts, flash voltages, AD questions   [3 Articles]

Lewis, Bob - Jun 10 2002
Hi Our MCU is the M68dg9128a eval brd, and works as long as the BDM cable is plugged in (the code is fully rom'd); how do we set this up to run without the bdm... BDM mode and ccts, flash voltages, AD questions

Re: Reset delay   [3 Articles]

William M. Derby Jr. - Jun 7 2002
Hi All, Is there any problems with the A4 in this regard. I have 5 boards and one will not reset out of a power up but will if the reset button is pushed. The ... Re:  Reset delay

Re: Errata list for 812A

Zámbó Béla - Jun 6 2002
Yes, I have. Best regards Béla Zámbó MOTOROLA MICROCONTROLLER DIVISION CUSTOMER ERRATA AND INFORMATION SHEET Part: HC812AV4.00K51E Rep... Re:  Errata list for 812A